hifi.slovanet.sk

[Krasomil]

SPDIF sam o sobe je pomerne nestastne reseni pro audio a je treba s nim zachazet velmi delikatne aby vysledek za neco stal. Dukazem budiz obecne znamy fakt, ze digitalni vystupy ruznych prehravacu (byt se stejnymi daty) hraji ruzne. Pro diy dac bude tento prepinac jiste dostacovat, koncepcne je vsak zapojeni spatne.

[dhaman]

Tak idem si po pivko bude zabava... sorry sa

[milandks]

a co je pricinou ?, nekvalitny, pripadne prenosovou cestou zdeformovany digitalny signal?, ten sa da predsa recoverovat ....
zaujimavym prikladom je pouzitie AD8611

PR: http://www.ettnet.se/~tobias/diy/sch.png


to krasomil: povodne zamyslane zapojenie je natolko jednoduche ze naozaj v DYI je pomerne lahko aplikovatelne ... co sofistikovanejsie odporucas?

istym "ne-automatickym" este jednoduhsim riesenim by bolo vyuzit vlastnost 8416ky a externym prepinacom zapojenym na vstup S0 ( pin 19 ) ovladat jej vnutorny prepinac a tak sa vyhnut urcitej degradacii signalu tym automatickym mechanickym relatkovym prepinacom ...

[FILIPAUDIO]

Použil bych dva sledovače, jeden prosignál a z druhého bych po galvanickém oddělení třeba optočlenem bral signál pro nějakou logiku.
U té 8416 pro jakékoliv logické vstupy i výstupy použij také optočleny, ulehčíš si tím život. Třeba až budeš na výstup převodníku dávat relé na MUTE, protože v případě kdy tam pustíš DTS z DVD přehrávače tak z výstupu poleze pěknej bordel
Použij pro to oba správně nastavené výstupy ERROR.

[L.V.]

[milandks]

este nejake zaujimave citanie o S/PDIF
http://www.positive-feedback.com/Issue14/spdif.htm
http://www.epanorama.net/documents/audio/spdif.html
http://peufeu.free.fr/audio/extremist_dac/spdif.html


zaujimava myslienka automatickeho resetingu DAC receivra ked sa u neho prepne signalovy digitalny vstup

http://sound.westhost.com/project85.htm

to filipaudio: dik za info s tym DVD, podla vyssie uvedenom linku by sa dalo trocha zmodifikovat zapojenie s rele na to aby sa cez ten signal ERROR dalo robit automaticke mute output DAC.

[milandks]

zakladna schema vstupneho modulu s CS8416, ktora sa este mierne upravi ...

[milandks]

inspiracia ako spravit kvalitny recovery clock pre DAC
( autor Jos van Eijndhoven )

How to ... PIC Software PLL for clock recovery
By browsing the net, it seems hard to find examples on how to implement a good PLL with a PIC microcontroller. Let me try to explain how I did so, and just discuss the global concept: your own PLL design would probably anyhow be somewhat different. Note that I do not intend to explain here how PLLs in general work: that is not quite easy, and beyond the scope of this page.

The goal of a clock recovery PLL is to create a high quality (read: very low jitter) clock signal from a lousy (noisy) input clock. 'Jitter' in a clock signal is the disturbance (error) in the supposedly uniform time period between successive (rising) edges of the clock signal. This 'jitter' has both an amplitude and a frequency aspect to it. To obtain good low-frequency jitter performance, the PLL as drawn above should adjust the VCXO clock frequency only slowly, and then only with small steps. Because we intend adjust the VCXO frequency only at low rate, the PIC has plenty of compute performance to implement a typical PLL low-pass filter.

The PIC operates itself on the clock of the VCXO. The 'dirty' input clock is routed to Timer0 in the PIC, which must be configured to run asynchronously. This Timer0 remains running, once enabled, and the firmware only reacts to the wrap-around moments, as flagged by the 'T0IF'.

The VCXO clock (the PIC internal clock) is passed to Timer1, which also continously keeps counting. The rate at which both counters do wrap-around is configured to be equal, by proper setting of the Timer0 prescaler. Every moment that T0IF gets set, the momentary value of Timer1 is captured. This is preferrably done as 'interrupt service routine', as it is important to have a constant (predictable) delay between the Timer0 wrap-around and the capturing of the Timer1 value. Note that neither counter is allowed to be stopped. If for example -as in my audio application- the VCXO runs at 11.289MHz (which is 256 x 44.1kHz, with 44.1kHz the digital audio sample rate), both counters wrap-around at approximately 43Hz (is 11.289MHz /4 /64K).

The captured value of Timer1 is a measure for the phase relation between both clock signals. (Or more accurate: for the phase relation between the divided-down 43Hz clocks). So at 43 Hz rate, the PIC computes the PLL low-pass filter on this 16-bit captured value, and sends the filtered result to the small serial-DAC to set the VCXO input.



Ina moznost by bola spravit digitalny pamatovy buffer vlozeny medzi prijimac a DAC a nahraty digitalny signal pustat do DAC podla presnych lokalnych hodin ...

[milandks]

a takto nejako koncepcne bude vyzerat moj buduci DAC 32-192KHz / 24bit

samostatne zdroje
samostatny prijimac
samostatny DAC
moznost volby I/V bud cez OZ alebo diskretny + moznost zapojit DC servo
moznost volby rezimu bitrate

[L.V.]

Pozerám, že na tom makáš. Držím palce.

[MiSt]

Ahoj,
ako pokračuješ v projekte ?

[milandks]

momentalne sa hrajem so zobrazovanim udajov na LCD 2*16 z 8416ky, udaje o navolenom vstupe a prijimanej frekvencii DAI ...

[MiSt]

Aha, takže si prešiel z HW mode CS4816 na ovládanie cez I2C alebo SPI prostredníctvom microprocesora.
Neuvažuješ v tvojom prototype s nejakým ASR (AD1896) ?

[milandks]

skorej ma laka AK4396

[MiSt]

Tak asi nebudem vymýšlať a spravím si tiež na začiatok niečo easy. Neskôr by som chcel sa trochu povenovať SRC4392 ale až keď budú nejaké skúsenosti s S-PDIF, i2s , a vecami okolo toho.

[milandks]

ja sa tiez ucim, mam to v SPI rezime co sa tyka prepojenia uP a CS8416
v HW mode je to ale easy na pokusy ako vysite...o)
m

[JTO]

Jasně, taky něco takovýho plánuju... a snad budu mít i kamaráda, co mi pomůže s programováním...

[MiSt]

Programovania sa naštastie nemusím obávať , už som niečo robil, ale to hlavne je naštudovať si jednotlivé chipy a ich režimy, či už prijímač alebo DA.

[milandks]

jednoduchy IV CFB stage